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ADE7518
LCD DRIVER
Using shared pins, the LCD module is capable of directly driving
an LCD panel of 17 × 4 segments without compromising any
ADE7518 functions. It is capable of driving LCDs with 2×, 3×,
and 4× multiplexing. The LCD waveform voltages are generated
through an external resistor ladder.
Each ADE7518 has an embedded LCD control circuit, driver, and
power supply circuit. The LCD module is functional in all operat-
ing modes (see the Operating Modes section).
LCD REGISTERS
There are six LCD control registers that configure the driver for
the specific type of LCD in the end system and set up the user
display preferences. The LCD Configuration SFR (LCDCON,
0x95), the LCD Configuration X SFR (LCDCONX, 0x9C), and
the LCD Configuration Y SFR (LCDCONY, 0xB1) contain general
LCD driver configuration information, including the LCD enable
and reset, as well as the method of LCD voltage generation and
multiplex level. The LCD Clock SFR (LCDCLK, 0x96) configures
timing settings for LCD frame rate and blink rate. LCD pins are
configured for LCD functionality in the LCD Segment Enable
SFR (LCDSEGE, 0x97) and the LCD Segment Enable 2 SFR
(LCDSEGE2, 0xED).
Table 67. LCD Driver SFRs
SFR Address
0x95
0x96
0x97
0x9C
0xAC
0xAE
0xB1
0xED
Mnemonic
LCDCON
LCDCLK
LCDSEGE
LCDCONX
LCDPTR
LCDDAT
LCDCONY
LCDSEGE2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
LCD Configuration (see Table 68).
LCD Clock (see Table 71).
LCD Segment Enable (see Table 74).
LCD Configuration X (see Table 69).
LCD Pointer (see Table 75).
LCD Data (see Table 76).
LCD Configuration Y (see Table 70).
LCD Segment Enable 2 (see Table 77).
Table 68. LCD Configuration SFR (LCDCON, 0x95)
Bit
7
6
5
Mnemonic
LCDEN
LCDRST
BLINKEN
Default
0
0
0
Description
LCD Enable. If this bit is set, the LCD driver is enabled.
LCD Data Registers Reset. If this bit is set, the LCD data registers are reset to zero.
Blink Mode Enable Bit. If this bit is set, blink mode is enabled. The blink mode is configured by the
BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96).
4
LCDPSM2
0
Forces LCD off when in PSM2 (sleep mode).
LCDPSM2 Result
0
1
The LCD is disabled or enabled in PSM2 by the LCDEN bit.
The LCD is disabled in PSM2 regardless of LCDEN setting.
3
CLKSEL
0
LCD Clock Selection.
CLKSEL Result
0 f LCDCLK = 2048 Hz.
1 f LCDCLK = 128 Hz.
2
BIAS
0
Bias Mode.
BIAS Result
0
1
1/2. In this mode, LCDVA is internally connected to LCDVB (see Figure 76).
1/3 (see Figure 77).
1 to 0
LMUX[1:0]
00
LCD Multiplex Level.
LMUX[1:0] Result
00 Reserved.
01
10
11
2× Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as FP28.
3× Mulitplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as COM2.
4× Multiplexing. FP27/COM3 is used as COM3. FP28/COM2 is used as COM2.
Rev. 0 | Page 81 of 128
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